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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIG-
NALING LINEARITY
5
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
V C
V C –
4 min
max
V DH =15V
T C = – 20 ~ 100?C
500 μ s
V C – (200%)
3
0V
V CH (5 μ s)
V CH (505 μ s)
V C0
2
V C +(200%)
r CH =
V CH (505 μ s)-V CH (5 μ s)
V CH (5 μ s)
1
0
Analogue output signal
data hold range
V C +
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 μ s delayed point.
–400 –300 –200 –100
0
100 200 300 400
Real load current peak value.(%)(I c =I o ! 2)
(Fig. 4)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal V CIN(p) of each phase upper arm
0V
Input signal V CIN(n) of each phase lower arm
0V
Gate signal V o(p) of each phase upper arm
(ASIPM internal)
Gate signal V o(n) of each phase upper arm
(ASIPM internal)
Error output F O1
0V
0V
0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O ” signal is outputted. After an “input
interlock” operation the circuit is latched. The “F O ” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal V CIN of each phase
upper arm
Short circuit sensing signal V S
0V
Gate signal Vo of each phase
0V
S C delay time
upper arm(ASIPM internal)
Error output F O1
0V
0V
Note : Short circuit protection operation. The protection operates with “F O ” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
May 2001
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